(a) Field of the Invention
The present invention relates to a waveform correction circuit and, more particularly, to a waveform correction circuit for use in a duty ratio correction circuit, which is capable of correcting a duty ratio of a pair of complementary signals such as two-phase clock signals. The present invention also relates to such a duty ratio correction circuit.
(b) Description of the Related Art
In a CMOSFET digital logic circuit, each of transmitted signals is generally a single-phase signal, which is different from a pair of differential signals such as used in a bipolar ECL circuit. In general, the single-phase signal involves a difference between a rise time and a fall time thereof due to a difference in the ON-resistance between the pMOSFET which is ON during the rise time and an nMOSFET which is ON during the fall time. This causes a time difference between the duration for a high level and the duration for a low level of the resultant signal, whereby the resultant signal has an irregularity or change in the duty ratio of the waveform. This is considered as one of the fundamental problems to be solved in a CMOS digital logic circuit.
FIG. 1 shows a timing chart of a pair of complementary signals xe2x80x9cAxe2x80x9d and xe2x80x9cA_xe2x80x9d having an ideal duty ratio of 5 wherein a concurrent signal transition is achieved between the complementary signals. That is, a rising edge xe2x80x9cArxe2x80x9d of the signal xe2x80x9cAxe2x80x9d is concurrent with a falling edge xe2x80x9cA_fxe2x80x9d of the signal xe2x80x9cA_xe2x80x9d, whereas a falling edge xe2x80x9cAfxe2x80x9d the signal xe2x80x9cAxe2x80x9d is concurrent with a rising edge xe2x80x9cA_rxe2x80x9d of the signal xe2x80x9cA_xe2x80x9d.
If these complementary signals xe2x80x9cAxe2x80x9d and xe2x80x9cA_xe2x80x9d are transferred by respective CMOSFETs, the resultant signals have a skew therebetween as well as a change in the duty ratio such as shown in FIG. 2, due to irregularities in the fabrication process of the semiconductor devices or a difference in the path length between the signals. In FIG. 2, the signal xe2x80x9cA_xe2x80x9d, for example, has a skew between the ideal falling edge (shown by dotted line) and the actual falling edge xe2x80x9cA_fxe2x80x9d, and a time difference Tcyc between the high-level duration and the low level duration. The time difference Tcyc causes an irregularity of the duty ratio deviating from 50% as indicated in FIG. 2 with reference to the ideal timing xe2x80x9cSxe2x80x9d,
A technique for synthesis of pair of signals having therebetween a skew is described in xe2x80x9cTechnical Digest of VLSI Circuit Symposium 1998xe2x80x9d. FIG. 3 shows the circuit configuration described in the publication, wherein outputs of a pair of inverters 11 and 12 each receiving one of clock signals xcfx861 and xcfx862 having the same clock frequency and a specific phase difference therebetween are connected for synthesis of waveforms or superposition. This provides an intermediate waveform having a median timing between both the clock signals xcfx861 and xcfx862 so long as the MOSFETs in both the inverters 11 and 12 have a specific difference in the transistor size therebetween.
More specifically, in FIG. 3, the MOSFETs in the inverter 11 receiving the signal xcfx861 which advances, for example, in phase with respect to the signal xcfx862 has a transistor size larger than the transistor size of the MOSFETs in the inverter 12 receiving the signal xcfx862. In other word, the MOSFETs in the inverter 11 has a lower output impedance compared to the MOSFETs in the inverter 12.
The configuration of FIG. 3 causes a penetrating current flowing between the inverters 11 and 12 during the time interval between the input of the signal xcfx861 and the input of the signal xcfx862. The difference in the transistor size as described above accelerates the operation of the MOSFETs in the inverter 11 having a larger transistor size to prevent the reduction in the switching speed caused by the penetrating current and accelerates the switch timing which may otherwise be delayed from the median timing.
In the described technique, it is generally necessary to determine beforehand as to which signal of the pair of signals xcfx861 and xcfx862 advances. If the signal xcfx862 advances with respect to the signal xcfx861 contrary to the designed circuit configuration, the circuit configuration cannot provide the intended operation.
In addition, the described technique is silent to the problem of the change in the duty ratio.
It is therefore an object of the present invention to provide a waveform correction circuit for use in a duty ratio correction circuit capable of correcting a pair of complementary signals as to the duty ratio and a skew thereof.
It is another object of the present invention to provide such a duty ratio correction circuit.
The present invention provides, in a preferred embodiment thereof, a waveform correction circuit including input and output terminals, first and second pMOSFETs, first and second nMOSFETs and a delay gate, the first pMOSFET and the first nMOSFET have gates connected together to the input terminal and drains connected together to the output terminal, one of the second pMOSFET and the second nMOSFET being connected between a first source line and a source of the first pMOSFET, the other of the second pMOSFET and the second nMOSFET being connected between a second source line and a source of the nMOSFET, the delay gate having an input connected to the input terminal and an output connected to the gates of the second pMOSFET and the second nMOSFET.
In accordance with the present invention, the waveform correction circuit has a lower output impedance during an initial stage after the signal transition of the input signal and a higher output impedance during a subsequent stage. The waveform correction circuit, if used in the circuit of FIG. 3, affords a suitable waveform for obtaining a median timing between clock signals xcfx861 and xcfx862 input through the first and second input terminals. The waveform correction circuit can be also used in a duty ratio correction circuit for correcting the duty ratio of a pair of complementary signals.
The present invention also provides a duty ratio correction circuit including a first circuit block for receiving a first input signal to deliver a first output signal, and a second circuit block for receiving a second input signal which is complementary with the first input signal to deliver a second output signal, each of the first and second circuit blocks including an input stage inverter for receiving one of the first and second input signal, a first inverter circuit for receiving an output from the input stage inverter, a second inverter circuit for receiving the other of the first and second input signals, and an output stage inverter having an input connected to outputs of the first and second inverter circuits.
In accordance with the duty ratio correction circuit, a pair of complementary signals can be corrected to have an improved duty ration and an improved timing for the signal transition.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.